FIG. 1 illustrates a programmable logic device 20 in accordance with the prior art. The programmable logic device 20 includes a set of logic array blocks 22. Row interconnect circuitry 24 and column interconnect circuitry 26 link the various logic array blocks 22. Input/output elements 28 positioned at the ends of the row interconnect circuitry 24 and column interconnect circuitry 26 are used for standard input/output operations.
FIG. 2 is a more detailed representation of a logic array block 22 in accordance with the prior art. The logic array block 22 includes a logic element stack 30, comprising a set of individual logic elements 31A-31H. A logic array block local interconnect circuit 32 routes signals into the logic elements 31. Column-to-row interconnect lines 34 and column-to-row interconnect logic 36 is used to route output signals from the logic elements 31 to the same or other logical array blocks 22.
FIG. 3 is a more detailed illustration of a prior art logic element 31. The logic element 31 includes a look-up table 40, which receives a set of data input signals. The look-up table 40 is programmed to implement a set of logic that is executed on the input signals. An output signal of the look-up table 40 is eventually routed to a register 42. The output signal is driven out of the register 42 in response to a clock signal from a clock control logic circuit 44. The clock control logic circuit 44 receives a set of input signals. Some of the signals are processed by a clear/preset logic circuit 46, while the other signals are processed by a clock selection multiplexer 48. The clock selection multiplexer 48 allows the register 42 to be driven by different clock signals. The output of the clock selection multiplexer 48 drives only a single register 42.
The clock control logic 44 is programmed into each logic element 31. Thus, in the logic element stack 30 of FIG. 2, clock generation circuitry is redundantly reproduced for eight logic elements 31. If this redundant circuitry could be reduced or eliminated, die space and processing costs could be reduced. In addition, inputs to the logic element may be used for combinatorial logic, instead of clock generation operations. Accordingly, it would be highly desirable to provide, from a single circuit, an enabled clock signal for application to all logic element registers within a logic array block of a programmable logic device.